Semiconductor integrated circuits have substantially increased in density in the past decade. However, there is an increasing demand for greater complexities, higher switching speeds and smaller devices for new applications, such as microprocessors and minicomputers. A very active area in the semiconductor fabrication technology has been the generation and application of fine lines in the lithographic technology. Light had been used almost exclusively until the recent past in the lithographic process. However, optical resolution limits make further advances in line widths much more difficult. The most important and versatile among the technologies for the future reduction in line widths are electron beam and X-ray exposure processes. The lithography problem and their possible solutions are discussed in greater detail by D. L. Critchlow in the publication entitled "High Speed MOSFET Circuits Using Advanced Lithography," published in the Computer, Vol. 9, No. 2, February 1976, pp. 31 through 37. In that publication the substantial equipment costs and complexities of X-ray and electron beam lithography are described.
There have been alternative efforts to obtain narrow line widths in the range of one micrometer or less by extending standard photolithography techniques and avoiding the need for the more expensive and complex techniques, such as electron beam or X-ray lithography. One such technique is descibed by H. B. Pogge in IBM Technical Disclosure Bulletin, November 1976, Vol. No. 6, entitled "Narrow Line Widths Masking Method." This method involves the use of a porous silicon followed by oxidation of porous silicon. Another technique is described by S. A. Abbas, et al., IBM Technical Disclosure Bulletin Vol. 20, No. 4, September 1977, pp. 1376 through 1378. This TDB describes the use of polycrystalline silicon masking layers which are made into masks by first using an intermediate mask of oxidation blocking material, such as silicon nitride in the formation of the polycrystalline silicon. Line dimensions below about two micrometers may be obtained by this technique. T. N. Jackson, et al., described "A Novel Submicron Fabrication Technique" in the March 1980 publication Semiconductor International, pp. 77 through 83, a method for producing submicron line widths and devices which do not require electron beam lithography but used a selective edge plating technique. The U.K. Pat. No. 2,003,660 published Mar. 14, 1979 describes a method for depositing an area of metal, for example metal on a substrate and forming narrow metal stripes thereby by using a unidirectional plasma etching technique. These above techniques do show ways of forming narrow lines on substrates but lack an overall solution for their successful use in the manufacture of semiconductor devices, because it is unclear how they will be used to contact actual device elements within the semiconductor substrate in an accurate and effective manner. Further, there are problems of planarity of the first level metallurgy and adequate conductivity of the metallurgy at that level. K. H. Nicholas, U.S. Pat. No. 4,083,098 describes a method of making a plurality of closely spaced, but air isolated, conductive layers on an insulated substrate. He suggests no ohmic connections to the silicon body under the insulator supporting his conductive layers.
The patent application of H. B. Pogge, Ser. No. 957,604 filed Nov. 3, 1978 now U.S. Pat. No. 4,256,514, entitled "Method for Forming a Narrow Dimensioned Region on A Body" and the patent application of J. Riseman Ser. No. 957,606 filed Nov. 3, 1978 now U.S. Pat. No. 4,234,362, entitled "Method for Forming An Insulator Between Layers of Conductive Material" describe a technique for forming narrow dimensioned, for example submicron, regions on a semiconductor body that involves forming on the silicon body regions having substantially horizontal surfaces and substantially vertical surfaces. A layer of the very narrow dimension is formed both on the substantially horizontal and substantially vertical surfaces. Reactive ion etching is applied to the layer to substantially remove the horizontal layer while leaving the vertical layer substantially intact. The vertical layer dimension is adjusted depending upon the original thickness of the layer applied. The patent applications more importantly describe techniques for using this narrowed dimensioned region in a semiconductor device fabrication process for various types of integrated circuit structures.
A major problem in very dense integrated circuits is the electrical contacts to the various elements and devices in the semiconductor integrated circuits. It is often necessary to have multilevels of metallurgy in the order of 2, 3, 4 or more levels of metallurgy to contact the large number of devices within the integrated circuits. These levels of metallurgy must be isolated from one another. This multilayer structure has the problems of planarity which can adversely affect the lithography process steps and result in defects in the structures through incomplete exposure of the lithographic layers. A further problem involves the conductivity of the metallurgy at the various levels. In recent times, solutions to these problems have taken the direction of the use of highly doped polycrystalline silicon as conductive layers such as shown in R. C. Wang, U.S. Pat. No. 3,750,268, issued Aug. 7, 1973 and R. T. Simko, et al., U.S. Pat. No. 3,984 ,822, issued Oct. 5, 1976. However, as the density of devices has increased, there still remains problems involving isolation between devices, conductivity particularly at the first level of metallurgy contacting the semiconductor devices, and alignment of the levels of metallurgy to the device elements in the semiconductor integrated circuit.
Circuits and structures utilizing integrated injection logic, sometimes abbreviated I.sup.2 L or referred to as merged transistor logic, abbreviated MTL, are well known in the integrated circuit arts. They may be understood in greater detail by reference to the Berger, et al. U.S. Pat. Nos. 3,643,235, 3,823,353 and 3,922,565. Such logic circuits or structures reduce a logic gate to a pair of merged complementary transistors in which a lateral PNP transistor is typically used as a current source for the base of an inverted NPN transistor. The NPN transistor, with a buried N type region as an emitter, will frequently have multiple collectors which may be used to drive other logic elements in a given circuit. I.sup.2 L circuits possess the inherent advantage of being compact because a logic gate is reduced to a single semiconductor device.
An object of this invention is to provide a greater density of I.sup.2 L circuits than ever thought to be possible.